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STM32H7 External 8mHz osc & PLL to 400mHz settings

Branyon Apel
Associate
Posted on July 07, 2018 at 10:37

Hi everyone,

I've been using the STM32H7 Nucleo board (STM32H743ZI) for a project I'm working on. I'm using plain CMSIS (no HAL solutions please ) and I'm having a bit of trouble setting the clock settings to use the external oscillator included on the board (8mHz). The initialisation function below is called from the main function on startup.

Running the software hangs and never cycles. Stepping through with the debugger causes it to drop the debug connection. It won't reconnect the next attempt either, it triggers a 'wrong target' error. Clearly I'm doing something wrong but I've spent a solid day pouring over the datasheet and I can't work out what the issue is. Wondering if anyone can see the issue?

*Edit* I followed the PLL initialisation flowchart (figure 44 pg. 329 STM32H743/753 reference manual)

Regards,

Branyon

void CLK_Init() {
 //Activate HSE
 SET_BIT(RCC->CR, RCC_CR_HSEON);
 //Wait till HSE Ready
 while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0) {
 __NOP();
 }
 //Use HSE External OSC (8mHz)
 CLEAR_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC_Msk);
 SET_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC_HSE);
 //Prescaler: /1
 CLEAR_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1_Msk);
 SET_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1_0);
 //Leave PLLxVCOSEL
 //PLL Range 4-8mHz
 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE_Msk);
 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE_2);
 //Fraction Default off
 //Enable clock output
 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
 //Multiply by 100
 CLEAR_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1_Msk);
 SET_BIT(RCC->PLL1DIVR, 0x63);
 //Divides by 2 by default
 //Activate PLL1
 SET_BIT(RCC->CR, RCC_CR_PLL1ON);
 //Wait till PLL1Ready
 while(READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0) {
 __NOP();
 }
 //Set System Clock to PLL
 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
 SET_BIT(RCC->CFGR, RCC_CFGR_SW_PLL1);
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#h7
4 REPLIES 4
Posted on July 08, 2018 at 16:21

Do you set up the flash wait states anywhere? AHB/APB clock dividers suitable for 400 MHz operation?

After you waste a day you might want to at least look at how a working HAL example functions, and the values that end up in the RCC/FLASH registers. You can choose to use whatever you want at the end of the day, but you're uphill skiing the problem here.

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Posted on July 10, 2018 at 05:05

The problem with a working HAL example is its so abstracted there is no easy way to access register set instructions. The best I've got is debugging and copying the RCC values down and duplicating those in my code (which is what I did so far as I can tell ). I'm unsure what you mean regarding the flash wait states, they weren't mentioned in the RCC section of the documentation? Is there another component that needs to be addressed?

I've used HAL enough to know a bit of extra time this end is better than the headaches as I progress. I've discovered the LL libraries for the lesser variants so I'm progressing with those (the F7 specifically) until the H7 LL's are released *hopefully* September. My code is (fingers crossed) easily portable.

dante11
Associate

The problem is, that the external quarz/cristal 8MHz (X3) and the two capacitances 4.3pF C37, C38, (0603)

are not on the board. All nucleo boards don't have these parts.

Look at mouser.com for NX3225GD-8.000M quarz and the two 4.3pFs.

You also have to solder (closing) the two bridge pads between the MCU and the quarz.

The next step is the terrible configuration. The cube sample doesn't work.

The H7 MCU is diffenent from the F7 MCU.

Have a lot of fun

Doesn't the ST-LINK provide an 8 MHz clock source?​

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