FAQ: STM32MP1 What ST offers to make a PCB design that ensures signal integrity ?

[Emmanuel COMBETTE DE RYMON]

DDR signals , DDR timings, PMIC BUCKs - what does ST provide to perform a PCB design with good signal integrity and DDR timings tuning  ?

The STM32MP1x DDR controller timings follows JEDEC standard.The timings are very standard timing across the brands. The Timing depends on the DDR type, DDR datasheet, clock frequency, the DDR topology (density) and the DDR speed Grade/bin.The DDR controller will apply strictly these timing that are described in JEDEC, they are not in the STM32MP1x data sheet.

For a successful design we recommend to re-use the Altium PCB layout projects provided in the ST evaluation boards or the Altium projects in the 'SMT32MP1 Serie DDR routing guideline examples' where different DDR topologies, different DDR types, different MP1 package are available. Signal integrity has been done on the DDR signals. Many customers follow this template and DDR in signal integrity issues are very seldom.

You have the MP1-DDR Layout examples zip file under 'Gerber files' : https://www.st.com/en/microcontrollers-microprocessors/stm32mp157.html#resource

Under the same link under the STM32MP1x IBIS model files are also available, in case signal integrity simulation is needed. AN4803 presents the usage of these IBIS model files.

You can find general rules to reach a signal integrity of your PCB written in the application note AN5122 STM32MP1x Series DDR memory routing guidelines.pdf and in the application note AN5431 STPMIC1 PCB layout guidelines.
 

The application note 'AN5168 DDR configuration on STM32MP1x Series MPUs.pdf' will provide more information on the DDR controller itself. This is for information only. The signal integrity are mostly guaranteed if the design follow recommended the length constraints and other tracks parameters computed in the Altium Layout examples. For each package, an excel sheet, in MP1-DDR Layout examples zip, provides the STM32MP1x internal length of the DDR signals. It helps to compute the total length of the tracks.

DDR timings are loaded in DDR controller registers by FSBL and the register values are located in the FSBL device tree files ( *.dtsi) files of TF-A binary.

To build these files, there are 2 possibilities:

-if the PCB contains a DDR3L@533Mhz you can re-use directly the ST reference boards (select the stm32mp15-ddr3-2x4Gb-1066-binG.dtsi or stm32mp15-ddr3-1x4Gb-1066-binG.dtsi according to your configuration). The timings can be applied for any DDR3L with the DDR Speed/bin Grade 1066-G .

-if your PCB uses another configuration, the STM32CubeMx will help you to compute the DDR timing configuration and will generate the device tree file relative to DDR settings.
 

Keyword Signal integrity , STM32MP1 IBIS model, DDR controller, JEDEC