FAQ: STM32 QSPI interface address in Dual-Flash memory mode

Document created by Jiri Vlcek Employee on May 29, 2018Last modified by Jiri Vlcek Employee on May 30, 2018
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Why does STM32 QSPI interface send addresses shifted right by 1bit in Dual-Flash memory mode?



The configured address in the QUADSPI_AR is divided by 2 (shifted right by 1bit) in DUAL bank mechanism, because each connected memory represents the half of the total size set in the FSIZE field. That’s why when writing data at a specific address, the QSPI peripheral outputs the half of the SW configured address.


The LSB bit of address represents specific flash:

  • even addresses are stored in Flash 1
  • odd addresses are stored in Flash 2


You can see write operations to addresses 0x20 and 0x21 in the picture.


qspi write operation